Nowadays, many electronic devices incorporate functionality that operates at radio frequencies, such as mobile communication devices. The implementation of such functionality in a cost-effective manner is far from trivial. It is well-known that bipolar transistors are particularly suitable for handling signals in the radio frequency (RF) domain. However, the manufacture of integrated circuits (ICs) based on silicon bipolar transistor technology is more costly than for instance complementary metal oxide semiconductor (CMOS) ICs, and the downscaling of the device feature size is more easily achieved in CMOS technology. The cost-effective nature of CMOS technology has led to the acceptance of CMOS technology as the mainstream technology of choice for the manufacture of a wide variety of semiconductor components including ICs.
However, the breakdown characteristics of CMOS transistors limit the usefulness of CMOS transistors in RF applications unless costly measures are implemented in the CMOS process to improve these characteristics. Such costly measures typically prohibit the use of RF-CMOS technologies for manufacturing small volume devices such as analog mixed signal (AMS) devices. For these reasons, efforts have been made to produce bipolar transistors using a CMOS process flow, thereby providing mixed technology ICs in which bipolar transistors can be used for handling RF signals. An example of such an IC is provided in WO2010/066630 A1.
The challenge that process developers face is that the number of alterations to the CMOS process should remain small whilst at the same time yielding good quality bipolar transistors that are capable of handling high frequency signals. An example of a low-complexity IC including a heterojunction bipolar transistor formed in a CMOS process flow can for instance be found in WO 2003/100845 A1.
An example of such a bipolar transistor is shown in FIG. 1, and comprises a silicon substrate 10 including an active region 11 in which the collector of the bipolar transistor is formed, e.g. by provision of a buried layer in the substrate 10 or by implantation of an impurity into the substrate 10. The active region 11 is defined in between isolation regions 12, e.g. shallow trench isolation (STI) regions. The bipolar transistor further comprises a layer stack including an epitaxially grown base layer, which grows as a monocrystalline region 14 over the silicon substrate 10 and as a polycrystalline region 14′ over the isolation regions 12. A nitride layer (not shown) may be present on the isolation regions 12 to promote epitaxial growth of the base layer portion 14′. A polysilicon base contact layer 16 is present on the base layer, which is covered by an electrically insulating layer 18. An emitter window 28 is defined over the active region 11, in which an emitter material 24 is formed, e.g. As-doped polysilicon, which is electrically insulated from the base contact layer 16 by sidewall spacers 22 in the emitter window 28 and by the electrically insulating layer 18 for the emitter material 24 deposited outside the emitter window 28, e.g. the emitter contact. The emitter material 24 is electrically insulated from the intrinsic base region 14 by further electrically insulation portions 20. The outdiffusion 26 of the emitter 24 is surrounded by these portions 20.
A complication in such mixed CMOS and bipolar transistor devices occurs when the device requires bipolar transistors for different purposes, such as high frequency as well as high voltage application domains. The optimized design parameters of a bipolar transistor for high frequency applications tend to differ from the optimized design parameters of a bipolar transistor for high voltage applications, as the increase in current gain that is desirable for high frequency applications, as it enables high cut-off frequencies and improved noise performance, is typically accompanied by a reduction in breakdown voltage, i.e. the open-base breakdown voltage BVCEO, due to the increased collector current density, which is highly undesirable in high voltage applications. There is therefore a need for a manufacturing method and IC in which this problem can be addressed.